VSD - Custom Layout

• 0
• 1
• 2
• 3
• 4
• 5

e. right from tech files to metal layer
Understand each and every mask level, through appropriate fabrication steps
Get to know how physical design flow communicates with CMOS fabrication process
This is how 2 different industries communicate
Requirements
Basic terms of CMOS, NMOS, PMOS
A brief summary of my existing course on 'Circuit design and SPICE simulations' will help, but can do even without that course
A brief knowledge of my existing courses on physical design flow and static timing analysis will also help
Description
Physical designers and CMOS fabrication team communicates with each other, and this course says it 'How'
While physical designers use all the outputs from expents performed by fabrication department, this course will demonstrate the best of both worlds and connect them through exchange of certain files in certain format
This way, custom layout designers get to know an insight how does fabrication works, fabrication eeers get to know, how layout eeers uses their information. So this course is a place where both meet, talk and connect.
Also, the standard files needed to draw and simulate layout, are being taken, deduced and created from scratch and on the fly. This is, by far, the best way to understand layout, and I can promise you an exciting journey throughout this course
Course is structured to explain the CMOS packaging and fabrication steps in bning, followed by software and files used to draw and simulate layout, and look into DRC rules.
Next, we will take a simple CMOS inverter and apply all concepts learned above. Finally, we will learn the 'Art of layout' using Euler's path. This is where you will solve complex functions and draw a layout out of it.
Welcome you all to my course and Happy Learning!!
See you in class!
Who this course is for
Anyone curious to know the inception of layout
Anyone curious to know the software behind layout drawing
Anyone who wants to know how chip designers talk with chip fabrication department

---

Related News

Digital Timing Basics For Vlsi Interview & Soc Design
Digital Timing Basics For Vlsi Interview & Soc Design MP4 | Video: h264, 1280x720 | Audio:... Autodesk MEP Fabrication Suite 2023.0.1 (Win x64)
Autodesk MEP Fabrication Suite 2023.0.1 | 3.2 Gb Autodesk Inc. is pleased to announce the... Ring VCO Design for PLL and DLL Applications
Ring VCO Design for PLL and DLL Applications Genre: eLearning | MP4 | Video: h264, 1280x720 |... Vsd - Mixed-Signal Risc-V Based Soc On Fpga
Last updated 7/2021 MP4 | Video: h264, 1280x720 | Audio: AAC, 44.1 KHz Language: English | Size:...

System Comment

Facebook Comment